1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more specifically, to a method for manufacturing a semiconductor device capable of preventing a mobile ion or moisture included in an interlayer insulation film from penetrating a semiconductor substrate.
2. Discussion of Related Art
In the process of manufacturing a semiconductor device, electric characteristics of the semiconductor device like a transistor can be deteriorated, when a mobile ion like hydrogen (H) is flowed in.
As a representative example, as shown in FIG. 1, a drain current (Idrain) may be increased abnormally in the region where a voltage is lower than a threshold voltage of a transistor. FIG. 1 is a graph showing the variation of the drain current according to voltage differences (Vgs) between a gate and a source.
Referring to FIG. 1, it is noted that, in the case of the characteristic graph of the transistor having a relatively long channel, an Idrain decreases drastically if Vgs between the gate and the source comes to be lower than a certain voltage. However, in the case of the characteristic graph of the transistor having a relatively short channel, it is also noted that an Idrain flows a lot abnormally, even though Vgs between the gate and the source comes to be lower than a certain voltage. This phenomenon described above is referred to Hump phenomenon, and the Hump phenomenon deteriorates refresh property in a DRAM device, or lowers credibility of the device or brings about inferior goods, by causing a malfunction in a Logic device.
To prevent the Hump phenomenon, as shown in FIG. 2, the penetration of H or moisture can be prevented by a diffusion protection film. FIG. 2 is a cross-sectional view of a transistor in accordance with an embodiment of the prior art.
Referring to FIG. 2, a transistor including a gate oxidation film 203, a gate 204, and a source/drain 205 is formed on a semiconductor substrate 201, conventionally. Subsequently, a diffusion protection film 207 is formed all over the upper part before forming an interlayer insulation film 208, wherein the diffusion protection film prevents H or moisture included in the interlayer insulation film from penetrating the semiconductor substrate. An insulation film spacer 206 is formed on the sidewalls of the gate 204.
Meanwhile, as described in FIG. 2, the upper part of the interlayer insulation film 208 is etched and the diffusion protection film on the upper part of the gate 204 is further etched, so that the upper surface of the gate could be exposed at the time of the subsequent chemical mechanical polishing process for flattening, even though the diffusion protection film 207 is formed between the interlayer insulation film and the transistor. Furthermore, the insulation film spacer 206 conventionally is formed to be a stacked structure having an oxide film and a nitride film, and in a case where the nitride film adjacent to the gate 204 is etched and the oxide film is exposed, the diffusion protection film 207 cannot perform its duty because H (or moisture) penetration path connected to the substrate 201 via the oxidation film of the insulation film spacer 206 from the interlayer insulation film 208 is formed.
For these reasons as described above, a capping layer is formed additionally as shown in FIG. 3, after performing the chemical and mechanical polishing process. FIG. 3 is a cross-sectional view of a transistor in accordance with an embodiment of another conventional art.
Referring to FIG. 3, after forming the interlayer insulation film 208 and performing the chemical and mechanical polishing process, the capping layer 209 is formed to prevent the gate 204 or the insulation film spacer 206 from being exposed. The capping layer 209 is formed as a film including a nitride like SiN.
As a result, as described in FIG. 4, the electrical characteristic of the transistor based on the threshold voltage variation can be improved by forming the capping layer 209. FIG. 4 is a graph showing the threshold voltage variation depending on whether the capping layer exists or not. Referring to FIG. 4, it is noted that the electrical characteristic of the transistor based on the threshold voltage variation is more improved when the capping layer is employed than not.
As described above, although by forming the capping layer including the nitride the electrical characteristic based on the threshold voltage variation can be improved, the problem may be generated that a leakage current characteristic comes to deteriorate. FIG. 5 shows the leakage current characteristic depending on whether the capping layer exists or not.
Referring to FIG. 5, it is noted that a junction leakage current is hardly generated in case of the capping layer not being formed, but generated in case of the capping layer formed.
Therefore, if a diffusion intestinal wall of the capping layer is directly contacted to the semiconductor substrate or the transistor, the junction characteristic deteriorates due to the nitride thereof, or the electrical characteristic of the device deteriorates due to the hot carrier degradation.